dule serial_pal(clka,clkb,da,wra_n,wrb,db);
input clka,clkb;
input da;
input wra_n;
output wrb;
output [7:0]db;
reg wrb=1'b0;
reg [7:0] db;
reg [7:0] data_out,data_out1,data_out2;
reg [3:0] cnt;
reg sel0,sel1,flag;
always@(posedge clka)
begin
    if(!wra_n)begin
        data_out<={data_out,da};
        cnt<=cnt+1'b1;
    end 
end

//
always@(posedge clkb)
begin
    if(wra_n)
      begin
       db<=data_out;
        wrb<=1;
     end
     else
        wrb<=0;
end
endmodule
